1. Field of the Invention
The present invention relates to a static RAM, and more particularly to a clock-synchronized SRAM with optimized timing of a driving control signal such as for the sense amplifier.
2. Description of the Related Art
Static RAM (hereinafter xe2x80x9cSRAMxe2x80x9d) comprises a latch circuit having cross-connected CMOS inverters in the memory cell and is a high-speed semiconductor memory which can retain stored data so long as power is applied. Data is continuously held by the latch circuit of the memory cell, making unnecessary periodic refresh operations such as in DRAM. Clock-synchronized SRAM is one of the types of high-speed SRAM developed in recent years. In this clock-synchronized SRAM, the address and control signal are supplied in synchronization with a clock, the internal circuitry operates according to the timing of the clock, and data are output after a prescribed access time from the supply of the clock.
Non-clock-synchronized SRAM does not have the clock supplied from outside, and instead, the internal circuitry is started upon the detection of a change of the input address.
The internal operations of SRAM are generally as follows. First, in the clock-synchronized type, an address input in synchronization with a clock is decoded and a word line is driven. With the driving of the word line, the memory cell drives a bit line and the voltage difference developed between bit lines is amplified by the sense amplifier. The data amplified by the sense amplifier are then output from the output buffer. When the reading operation is complete, the bit line pair and sense amplifier output pair are short circuited and precharged to the power supply voltage.
All of the operations above are controlled by a timing control signal generated by a timing control circuit. In particular, the sense amplifier enable signal is preferably generated at the shortest time after the bit line is driven by the memory cell and the prescribed voltage difference is developed between bit lines. The driving capability of the memory cell varies according to the process variation. Accordingly, the sense amplifier control signal is generated with a sufficient timing margin from the activation of the word line. Even if the driving capability of the memory cell varies into lower and the time at which the prescribed potential difference is developed between bit lines is delayed, the sense amplifier does not operate in error due to this timing margin.
The high-speed characteristics of SRAM are lost when sufficient margin is established in the timing of the bit line enable signal as discussed above. A proposed method for resolving this problem is a self-timing system wherein a dummy circuit, with a word line, memory cells, and bit lines, is provided and the sense amplifier enable signal is generated using this dummy circuit.
FIG. 1 shows a schematic of conventional SRAM using such a dummy circuit. In this example, the address Add and control signal Cont input in synchronization with the clock CK are decoded by the timing control circuit and decoder circuit 14, and the timing signals EQB, CS, EQ, and OE are generated. The word line WL selected by the decoder circuit is driven by the word line driver 12 and selects a memory cell MC in the memory cell array 10. In response thereto, the memory cell MC drives the bit line pair BL, BLX and the bit line pair selected by the column switch 18 is amplified by the sense amplifier 20. The sense amplifier output SO, SOX is latched by the output latch circuit 24 at the time of the output enable signal OE and output to the output buffer 26 through the output lines OL, OLX, and the output data Dout are generated. After that, the bit line pair is short circuited by the bit line equalizing circuit 16 at the time of the bit line equalizing signal EQB and precharged to the power source voltage. In the same way, the sense amplifier output So, SOX is also short circuited and precharged at the time of the equalizing signal EQ. When writing, the input data Din is input to the input circuit and write amplifier 28, and the selected bit line pair is driven from the write amplifier.
In this prior art, a dummy word line DWL is provided separately from the word line WL in the memory cell array 10; the dummy memory cells DMC are provided separately from the regular memory cells MC, and the dummy bit line pair DBL, DBLX is provided separately from the regular bit line pair BL, BLX. A loading dummy cell DMCW is provided on the dummy word line DWL and a loading dummy cell DMCB is provided on the dummy bit line pair DBL, DBLX. Accordingly, the dummy word line DWL is driven when the regular word line WL is driven and, at the time when the prescribed voltage difference is generated across the regular bit line pair, the same voltage difference is generated across the dummy bit line pair DBL, DBLX. Consequently, the SE timing circuit 30 generates the sense amplifier enable signal SE in response to the voltage difference on the dummy bit line pair DBL, DBLX and can thereby start the sense amplifier 20 at the optimum timing.
Even when the driving capability of the memory cell varies because of the process variation, the sense amplifier enable signal SE can be generated at the optimum timing corresponding to those process variation because the same variation occur in the dummy memory cell DMC.
A problem of the prior art discussed above is that since the dummy circuit, comprising a dummy word line DWL, a dummy memory cell DMC, and dummy bit line pair DBL, DBLX, is accessed each cycle, the reliability of transistors and wiring in the dummy circuit is lower than that of the regular circuit, comprising a word line, memory cells, and bit line pair. For example, if there are 512 word lines WL in the memory cell array 10, the probability that a regular word line WL will be operating is 1/512. On the other hand, because the dummy word line DWL is accessed each cycle, the probability of the driving operation is 1. The dummy word line is driven at a high frequency and consequently, the transfer gate transistors in the dummy memory cell controlled by the dummy word line is controlled in a conductive state every cycle by the driving of the dummy word line. Because of this control, the transfer gate transistors have decreased its driving capability because of hot carrier deterioration and the like so that the timing of the sense amplifier enable signal SE generated by the dummy circuit will be delayed.
Furthermore, the prior art discussed above results in greatly increased power consumption because the dummy circuit operates every cycle and the dummy word line is driven separately from the regular word line. In effect, during normal operations, the regular word line WL is driven along with the dummy word line DWL, and as a result the power consumption increases.
FIG. 2 shows the constitution of another conventional SRAM using a dummy circuit. The same reference numbers are used as in FIG. 1. In this prior art, a dummy word line is not provided and all the regular word lines WL are connected to the dummy memory cells DMC provided on the left side of the memory cell array 10. Consequently, the dummy memory cells DMC are positioned along the dummy bit lines DBL, DBLX and are disposed in the same way as the regular memory cells MC.
Because the dummy word line is omitted from this example, the increase in power consumption can be suppressed by a corresponding degree. Moreover, the decrease in reliability can be prevented because the dummy memory cells DMC are not accessed every cycle.
However, because every word line is connected to a dummy memory cell, the dummy memory cells DMC must be provided at the same pitch as the regular memory cells MC. Even if the dummy bit line pair DBL, DBLX is driven by a plurality of dummy memory cells DMC, the driving operation cannot be made faster than that of the regular bit line pair BL, BLX and it becomes difficult to provide optimum timing of the sense amplifier enable signal SE. In effect, in order to generate the sense amplifier enable signal SE at the optimum time, the change in voltage of the dummy bit line pair supplied to the SE timing circuit is preferably made somewhat faster than the change in voltage of the regular bit line pair. In order to make the operation of the dummy bit line pair faster than that of the regular bit line pair, the driving capability of the dummy memory cell must be made greater than that of the regular memory cell. However, such a constitution is difficult in the example in FIG. 2 where dummy memory cells DMC are provided to every word lines WL.
Adding the dummy memory cells DMC in a direction parallel to the word lines WL was considered as a countermeasure, but the load capacity of the dummy bit line pair becomes higher with such positioning and such high speeds cannot be achieved.
It is therefore an object of the present invention to provide SRAM having a dummy circuit which can generate a control signal at the optimum timing and has low power consumption.
It is another object of the present invention to provide SRAM having a dummy circuit which can make small adjustments to the timing of the control signal and generate a control signal at the optimum timing corresponding to a process variation.
In order to achieve the abovementioned objects, one aspect of the present invention is a static RAM comprising a memory cell array having memory cells located at intersections of word lines and bit lines, and a sense amplifier for amplifying a voltage of the bit lines; this static RAM further comprising: dummy memory cells selected when the word line is selected; a dummy bit line connected to the dummy memory cells; a timing signal generating circuit for generating a timing control signal in response to a change in potential of the dummy bit line; and a dummy memory cell selecting circuit for, in response to a selection of a word line in a word line group including a plurality of the word lines, selecting the dummy memory cell shared by the word line group.
In the abovementioned invention, the plural word lines in the word line group share the dummy memory cell and the corresponding dummy memory cell is selected in response to the selection of any word line in the word line group. When selected, the dummy memory cell drives the dummy bit lines and causes the potential thereon to change. The timing signal generating circuit at least generates a sense amplifier enable signal for starting the sense amplifier in response to the change in potential of the dummy bit lines. As a result, first of all, the dummy word line can be omitted and the increase in power consumption therefore can be suppressed. In the second place, having a shared dummy memory cell for a plurality of word lines makes it possible for a plurality of dummy memory cells to be selected at the same time and to generate the sense amplifier enable signal at the optimum time.
In a more preferable embodiment of the abovementioned invention, the dummy memory cells have the same dimension as the regular memory cells and are connected in parallel to the dummy bit lines. Furthermore, a dummy cell unit is constituted by a plurality of dummy memory cells and the dummy memory cells associated with the dummy cell unit are selected at the same time. Because the plurality of dummy memory cells is selected at the same time according to the above structure, the dummy bit lines can be driven at a high driving capability and consequently the change in potential of the dummy bit lines can be made faster than for the regular bit lines. Consequently, the timing signal generating circuit can generate the sense amplifier enable signal at more appropriate timing. Moreover, the dummy memory cells can be realized in a layout identical to that of the regular memory cells.
In a more preferable embodiment of the abovementioned invention, the dummy memory cell comprises a latch circuit having two cross-connected inverters, with one of a pair of nodes of the latch circuit being connected to a high level or low level power source. With such a structure, the driving direction of the dummy bit line pair by the dummy memory cells is always the same direction and the structure of the timing signal generating circuit can be simplified. In particular, when a plurality of dummy memory cells in a dummy cell unit are selected at the same time, one of the pair of nodes of the latch circuit in the dummy memory cells is connected to the same level power source and therefore, the driving directions of the dummy bit line pair at the time of selection are all same. The competitive operation among the plurality of simultaneously selected dummy memory cells is thereby prevented.
In a more preferable embodiment of the abovementioned invention, the plurality of word lines provided in the memory cell array are divided into a plurality of word line groups and a plurality of dummy memory cell selecting circuits are provided for the word line groups respectively. By having a plurality of dummy memory cell selecting circuits in this way, it becomes possible to reduce the number of word lines input to each of the dummy memory cell selecting circuits and the scale of the dummy memory cell selecting circuits can be kept small.
In a more preferable embodiment of the abovementioned invention, a dummy cell unit setting circuit is provided for variably setting the number of dummy memory cells associated with the dummy memory cell unit. First of all, this dummy cell unit setting circuit has a structure wherein the number of dummy memory cells in a single dummy memory cell unit can be set variably by a control signal from outside. As an another structure, the number of dummy memory cells can be set variably by a storage signal of ROM disconnectable by a laser beam or the like. As further another structure, the number of dummy memory cells can be set variably by a metal option through the mask pattern of the wiring layer.
In order to achieve the abovementioned objects, another aspect of the present invention is a static RAM wherein an address is supplied in synchronization with a clock; this static RAM comprising: a memory cell array having memory cells located at intersections of word lines and bit lines; a sense amplifier for amplifying a voltage of the bit lines; dummy memory cells selected when the word line is selected; a dummy bit line connected to the dummy memory cells; a timing signal generating circuit for generating a timing control signal in response to a change in potential of the dummy bit line; and a dummy memory cell selecting circuit for inputting a word line group including a plurality of the word lines and selecting the dummy memory cell shared by the word line group in response to a selection of at least one of the word lines in the word line group.
In order to achieve the abovementioned objects, another aspect of the present invention is a static RAM wherein an address is supplied in synchronization with a clock and the operation cycle is controlled by the clock; this static RAM comprising: a memory cell array having memory cells located at intersections of word lines and bit lines; a sense amplifier for amplifying a voltage of the bit lines in response to a sense amplifier enable signal; a plurality of dummy memory cells aligned with the memory cell array and disposed in the direction of the bit lines; a dummy bit line connected in parallel to the plurality of dummy memory cells; a timing signal generating circuit for generating the sense amplifier enable signal in response to a change in potential of the dummy bit line; and a dummy memory cell selecting circuit for selecting a plurality of the dummy memory cells at the same time in response to the selection of the word line.